LC-3 ISA: memory, registers, operate and data movement instructions

Weeks 7 and 8 are the center of the course: the instruction set (ISA) of the LC-3. Everything you have learned so far comes together here: 2’s complement (offsets), sign extension (imm5), the decoder (opcode), mux and register (data path), the instruction cycle (phases). On this page you see the structure of the LC-3, the operate instructions that do calculations, and the data movement instructions that carry data between memory and registers. Branches and loops are in week 8.

Question types on the exam: translate an instruction into 16-bit machine code (encode), translate a hex value into an instruction (decode), compute the effective address, trace a short program and write the register values and condition codes.

The structure of the LC-3

User programs usually start at x3000. x0000-x00FF is the trap vector table, xFE00 and above are the device registers (week 6).

Condition codes

Every instruction that writes a value into a register (ADD, AND, NOT, LD, LDI, LDR) sets one of three bits to 1 according to the value written:

Instructions that write to memory (ST, STI, STR) and branch instructions do not change the condition codes. In week 8 the BR instruction will decide by looking at exactly these bits.

PITFALL · LEA and the condition codes. In the 2nd edition of the textbook (the book of this course) LEA also sets the condition codes; in the 3rd edition it does not. If you see a BR right after an LEA in the exam, pay attention to which rule the instructor uses; the safest thing is to put the instruction that actually writes the value before the BR.

Opcode table

Operate instructions: ADD, AND, NOT

ADD and AND have two forms. Bit 5 tells which one it is.

register mode:   op  | DR  | SR1 | 0 | 00 | SR2
                 15-12 11-9  8-6   5   4-3  2-0
immediate mode:  op  | DR  | SR1 | 1 | imm5
                 15-12 11-9  8-6   5   4-0
NOT:             1001| DR  | SR  | 111111

• ADD R5, R1, R3: R5 ← R1 + R3.
• ADD R3, R1, #-4: R3 ← R1 + SEXT(imm5). imm5 = -4 = 11100, extended to 16 bits as 1111 1111 1111 1100.
• NOT R1, R1: flips every bit of R1.

The range of imm5 is -16..+15. If you need a larger constant, you have to put it in memory with .FILL and load it with LD.

Encoding example

AND R4, R3, #15:

0101 | 100 | 011 | 1 | 01111
AND    R4    R3    imm  +15
0101 1000 1110 1111 = x58EF

Ready-made patterns

The result of NOT alone is $-x - 1$: NOT 7 = -8. Do not forget to add +1.

Addressing modes

Where can an operand be? In the LC-3 there are five answers:

LEA also computes PC + offset9 but does not read memory; it puts the address itself in the register.

PC-relative: LD and ST

LD/ST:  op | DR/SR | PCoffset9
address = (incremented PC) + SEXT(PCoffset9)

The PC is used in its incremented form. If the instruction is at x3010, when FETCH finishes PC = x3011. The offset is added to this. The offset is 9 bits, range -256..+255: an instruction can access about 256 locations near itself.

LD R2, #-5 at x3010: address = x3011 - 5 = x300C.

0010 | 010 | 1 1111 1011 = x25FB
LD     R2    -5

PITFALL · adding the offset to the instruction’s own address. Whoever writes x3010 + (-5) = x300B loses points. The PC had already been incremented by one in FETCH: x3011 + (-5) = x300C.

Indirect: LDI and STI

An address is stored in memory. First that address is read, then the data at that address.

LDI R3, #2 (at x3000)
1) x3001 + 2 = x3003       M[x3003] = x4000   (this is a pointer)
2) M[x4000] = x0042  →  R3 = x0042

This is the way to reach far addresses (for example the device registers at xFE00).

Base+offset: LDR and STR

LDR/STR:  op | DR/SR | BaseR | offset6
address = BaseR + SEXT(offset6)      range -32..+31

Because the base register is 16 bits, any place in memory can be reached. Arrays, the stack and pointers work with this mode (you will see them in the C weeks).

With STR R2, R5, #-1 and R5 = x4001, R2 = x00AA → M[x4000] = x00AA.

LEA: load the address

LEA R1, ARR → R1 ← the address of ARR. Memory is not read. To get the starting address of an array, use LEA, then access the elements with LDR:

        LEA  R1, ARR       ; R1 = x3005 (the address of ARR)
        LDR  R2, R1, #2    ; R2 = ARR[2] = 10
        LDR  R3, R1, #0    ; R3 = ARR[0] = 7
        ADD  R4, R2, R3    ; R4 = 17
        HALT
ARR     .FILL #7
        .FILL #-2
        .FILL #10

Decode recipe

1. Expand the hex to 16 bits.
2. The first 4 bits are the opcode, look at the table.
3. According to the format of the opcode, split the remaining 12 bits into fields.
4. If there is an offset, sign-extend it, and if an address is needed, add it to the incremented PC.

Example: x2A10, at address x3100.

0010 101 0 0001 0000
LD   R5  PCoffset9 = 0 0001 0000 = +16
address = x3101 + 16 = x3101 + x10 = x3111
→ LD R5, x3111    (R5 ← M[x3111])

Example: x7F3F.

0111 111 100 111111
STR  R7  R4  offset6 = 111111 = -1
→ STR R7, R4, #-1    (M[R4 - 1] ← R7)

Worked trace

        .ORIG x3000
        LD   R1, A        ; R1 = 13
        LD   R2, B        ; R2 = -6
        ADD  R3, R1, R2   ; R3 = 7
        AND  R4, R3, #7   ; R4 = 7
        NOT  R5, R4       ; R5 = -8
        ST   R3, C        ; M[C] = 7
        HALT
A       .FILL #13
B       .FILL #-6
C       .BLKW 1
        .END

The machine code the assembler produced:

x3000  x2206   LD  R1, A      (x3001 + 6 = x3007 = A)
x3001  x2406   LD  R2, B      (x3002 + 6 = x3008 = B)
x3002  x1642   ADD R3, R1, R2
x3003  x58E7   AND R4, R3, #7
x3004  x9B3F   NOT R5, R4
x3005  x3603   ST  R3, C      (x3006 + 3 = x3009 = C)
x3006  xF025   HALT
x3007  x000D   A = 13
x3008  xFFFA   B = -6
x3009  x0000   C

Result: R3 = 7, R4 = 7, R5 = xFFF8 (-8), M[x3009] = 7. The last instruction that set the CC is NOT (R5 is negative) → N. ST did not change the CC.

Common mistakes

        .ORIG x3000
        LD   R1, A
        LD   R2, B
        ADD  R3, R1, R2
        AND  R4, R3, #7
        NOT  R5, R4
        ST   R3, C
        HALT
A       .FILL #13
B       .FILL #-6
C       .BLKW 1
        .END